Keynote Talks
Memory-Centric Computing: Solving Computing's Memory Problem
Prof. Onur Mutlu
ETH Zürichn
Computing is bottlenecked by data. Large amounts of application data overwhelm the storage capability, communication capability, and computation capability of the modern machines we design today. As a result, many key applications' performance, efficiency, and scalability are bottlenecked by data movement. In this talk, we describe three major shortcomings of modern computers in terms of 1) dealing with data, 2) taking advantage of vast amounts of data, and 3) exploiting different semantic properties of application data. We argue that an intelligent computing architecture should be designed to handle data well. We posit that handling data well requires designing architectures based on three key principles: 1) data-centric, 2) data-driven, 3) data-aware. We give examples of how to exploit these principles to design a much more efficient and higher performance computing system. We especially discuss recent research that aims to fundamentally reduce memory latency and energy, and practically enable computation close to data, with at least two promising directions: 1) processing using memory, which exploits the fundamental operational properties of memory chips to perform massively-parallel computation in memory, with low-cost changes, 2) processing near memory, which integrates sophisticated additional processing capability in memory chips, the logic layer of 3D-stacked technologies, or memory controllers to enable near-memory computation with high memory bandwidth and low memory latency. We show both types of architectures can enable order(s) of magnitude improvements in performance and energy consumption of many important workloads, such as artificial intelligence, machine learning, graph analytics, database systems, video processing, climate modeling, genome analysis. We discuss how to enable adoption of such fundamentally more intelligent architectures, which are key to efficiency, performance, and sustainability. We conclude with some research opportunities in and guiding principles for future computing architecture and system designs.
An accompanying overview of modern memory-centric computing ideas & systems can be found at "A Modern Primer on Processing in Memory", updated February 2025.
A shorter invited paper from IMW 2025 is at "Memory-Centric Computing: Solving Computing’s Memory Problem", May 2025.
Beyond the Dot Product: Reimagining What Memory Can Compute
Prof. Kaushik Roy
Purdue University
Compute-in-memory (CiM) has emerged as a promising paradigm for overcoming the energy and performance costs of data movement, with most efforts focused on accelerating matrix–matrix multiplication—the computational backbone of modern AI. This talk explores how we can extend the capabilities of memory well beyond dot-product operations to support a broader range of computations required by emerging workloads. In particular, I will discuss performing nonlinear and transcendental functions, such as softmax and GELU, directly within memory. A key idea is to overlay read-only memory (ROM) onto existing RAM arrays by encoding ROM data through hard-wired connectivity, enabling lookup-table-based computation with essentially no additional array-level area overhead. I will also discuss how intrinsic device and circuit stochasticity can be harnessed within CiM to efficiently address combinatorial optimization problems. Together, these directions point toward a broader vision of memory evolving from a passive storage element into a versatile computational substrate capable of linear, nonlinear, and stochastic computation.
Invited Industrial Talks
In-Memory Computing for Efficient AI: From Edge Inference to Large-Scale Systems
Dr. Irem Boybat
IBM Research Europe - Zurich
AI is placing rapidly growing demands on computing hardware, from compact edge devices to large-scale systems serving large language models. Across this range, moving data between memory and processing units dominates energy consumption and limits performance. In-memory computing (IMC) addresses this bottleneck by performing matrix-vector multiplications directly within memory arrays. Realizing its benefits for real workloads, however, requires more than efficient arrays: it calls for co-design across the full stack, from circuits and system architecture to the software that maps workloads onto the hardware. This talk explores IMC-based AI inference across this stack and across deployment scenarios. For edge inference, we discuss heterogeneous architectures that integrate IMC with programmable digital accelerators, together with the periphery design, mapping, and scheduling needed to deploy modern neural networks efficiently, as well as domain-specific designs for edge applications. We then turn to large-scale systems, where scaling IMC into the third dimension offers a path toward the density needed to serve large language models efficiently. We conclude with an outlook on the software support needed to make IMC accelerators programmable and deployable, and on the open challenges and opportunities in bringing IMC from research prototypes to practical AI systems.
